In recent years, 3-dimensional and 2.5-dimensional stacked semiconductor devices incorporating a plurality of interconnected semiconductor substrates (chips) stacked therein has gained attention in terms of higher performance of the semiconductor device. In manufacturing of the stacked semiconductor device, in order to connect the densely spaced fine wirings of the substrates with each other, the semiconductor substrates are bonded to each other using a micro-bump configured with a solder layer and a barrier layer.
When the number of stacked layers of the semiconductor substrates is increased, the thickness of the stacked semiconductor device (package) is increased. In order to reduce the thickness of the stacked semiconductor device, it is necessary to reduce the distance between the adjacent semiconductor substrates. In order to reduce the distance between semiconductor substrates, in the related art, the amount of solder used to interconnect the adjacent substrates is reduced. However, when the amount of solder is excessively small, the solder alloys with the barrier layer, such that it is difficult to maintain un-alloyed solder required for bonding together the wirings of the semiconductor substrates.
Therefore, in the stacked semiconductor device, there is a need to reduce the thickness of the semiconductor device and to appropriately bond semiconductor substrates (chips) with each other.